Proliferation of battery-powered portable personal computers and increasing public awareness of practical and environmental issues related to energy conservation may create a demand to conserve power in computing devices. For portable computers, thermal management and battery longevity concerns drive power conservation efforts. In desktop computing devices, power conservation relates to conserving natural resources in keeping with government and industry standards such as EPA's EnergyStar standard.
Portable computers may only be useful if battery life supports a reasonable period of use between charges. Sufficient periods of time may be necessary to allow users to complete lengthy tasks or series of tasks. Modern portable computer batteries, even when rated for eight hours of use, may have lives of only about two or three hours between charges when continuously running CPU intensive tasks. Additional concerns regarding thermal runaway may be compounded in a high clock speed environment during extended periods of heavy processing loads.
Clock speed is known in the art to have a direct relationship to power consumption. Lee, et al., U.S. Pat. No. 5,254,888, issued on Oct. 19, 1993 and incorporated herein by reference discloses an Intel 486 CPU operating at 33 MHz may dissipate about 4 watts of power. Lee, et al. discloses a technique for saving power by slowing the clock during wait states. However, the technique disclosed in Lee may not accomplish selective application of a clock stopping signal within programmed intervals while the system may be in one of several power conservation modes.
Modern operating environments such as Microsoft.RTM. Windows.RTM. with graphical user interfaces (GUI), even when idle, may require more processing from the CPU than non-GUI based operating systems. Thus, a portable computer which is running a GUI based operating system may experience shorter battery life when idle than its idle non-GUI counter part. Other system components such as displays, disk drives, and keyboards consume system power when accessing processor resources. Reducing power consumed by these system components while maintaining the ability to monitor their activity and provide them with processing resources without delay may be desirable.
Prior art power conservation methods such as sleep modes which disable the processor more completely, may have the disadvantage of long wake-up latencies. Service to system peripherals may not be possible until full processor wake-up. Providing system peripherals with faster access to processor service may shorten wake-up latency. Shortening wake-up latency may translate to more tolerable wait times for the user as the system wakes up. Moreover, some processing requests may be serviced in the background without requiring full wake-up. By making it possible for some activity to be processed during sleep modes, a wider array of activity may be available to trigger wake-up.
Interrupts are known in the art and may be generated when system activity is present either from user input or from peripherals which require processor service. Peripheral devices may request service from a processor through an interrupt request. Interrupt requests may be serviced through the execution of an Interrupt Service Routine (ISR). When an interrupt occurs, the processor stops executing a present program and begins executing the ISR as discussed in Chapter 18, pp 331-366, ISA System Architecture, Shanley and Anderson, MindShare Press, 1991, 1993, incorporated herein by reference. The processor may respond to an interrupt request and determine which device or software process initiated the request by obtaining the associated interrupt number. Once the identity of the interrupt is determined by interrupt number, the address of the ISR may be found from the interrupt vector table (IVT) and the ISR executed. When the ISR is finished executing, execution may resume at the location stored when the processor was interrupted.
Interrupts may be generated from system activity related to keyboard input, disk drive access, peripheral access, and other system events. Conversely, other interrupts may be indicative of system inactivity. ISRs for software interrupts may be programmed into BIOS ROM and loaded into corresponding interrupt number entries in the IVT at startup. The IVT may reside in the real mode address space 00000H to 003FFH. In protected mode, the IVT can be relocated anywhere in memory.
Some prior art systems perform selective memory transaction monitoring as in Stager, et al., U.S. Pat. No. 5,377,344 issued on Dec. 27, 1994, and store values in a shadow RAM. Storing values in a RAM is well known in the art. Garney, U.S. Pat. No. 5,386,552 issued Jan. 31, 1995, discloses a system to preserve the processing state in a mass storage system. In Garney's system, a shadowed interrupt vector does not appear to be disclosed as a nap triggering event nor does any interrupt appear to be disclosed as a nap triggering event.
Common DOS fixed software interrupt INT16H, for example, is well known. Interrupt INT16H, known as the Keyboard Services interrupt is described in The Proarammer's PC Sourcebook, 2nd Ed., Tom Hogan, Microsoft Press, 1991, incorporated herein by reference. When there is no input from a user, DOS may loop on INT16H looking for keyboard activity. Detecting such system looping on INT16H in itself may be used to trigger sleep modes. Subsequent activity may trigger a system to wake up. However, as described earlier, an often prolonged period must be endured for the system to wake-up in order to begin or resume a task. Then, when processing is restored, all processing resources may be available.
Such an approach may be inefficient since a demand for immediate processing may be present once wake-up activity is detected by the wake-up event itself. Other system events or activity may demand immediate processing but for a short period of time, while still other system events or activity may call for processing of a background nature. Moreover, there may be small intervals between events too small to activate sleep modes but susceptible to being used to achieve a power savings. During such relatively short time intervals where full processor resources may be available, there may not be a corresponding need for processing.